EDI2CG472128V
White Electronic Designs
ADVANCED
BURST ADDRESS TABLE (MODE=NC/VCC
)
BURST ADDRESS TABLE (MODE=GND)
First
Second
Address
(internal)
A-A01
A-A00
A-A11
A-A10
Third
Fourth
First
Second
Address
(internal)
A-A01
A-A10
A-A11
A-A00
Third
Fourth
Address
Address
Address
Address
Address
(external)
A-A00
Address
(external)
A-A00
(internal)
A-A10
A-A11
A-A00
A-A01
(internal)
A-A11
A-A10
A-A01
A-A00
(internal)
A-A10
A-A11
A-A00
A-A01
(internal)
A-A11
A-A00
A-A01
A-A10
A-A01
A-A10
A-A11
A-A01
A-A10
A-A11
READ CYCLE TIMING PARAMETERS
8.5ns
Max
10ns
Max
12ns
Max
15ns
Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
Sym
tKHKH
Min
Min
15
5
Min
15
5
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
20
6
6
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
5
5
10
12
15
3
4
3
4
3
4
5
5
5
5
6
0
0
0
5
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
*TBD
SYNCHRONOUS ONLY READ CYCLE
t
KHKH
t
KLKH
t
KHKL
CK
t
AVKH
Ex#
Addr 1
Addr 1
Addr 2
ADDR
t
KHAX
t
KHQV
G#
GW#
DQ
t
GLQV
t
GLQX
t
KHQX
Q(Addr 1)
Q(Addr 1)
Q(Addr 2)
t
KHQZ
t
KHQX1
Read Cycle
Back to Back Read
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
