PCMCIA Flash Memory Card
FLV Series
White Electronic Designs
PINOUT
Pin
35
36CD
37
38
39
40
41
42
43
44
45
46A
47
48
49
50
51
52
53
54
55
56A
57
58
59
60
61
62
63
6
Signal name
GND
1
I/O
Function
Ground
Card Detect 1
Data bit 11
Active
Pin
1
2
Signal name
I/O
Function
Ground
Data bit 3
Active
GND
DQ3
DQ4
DQ5
DQ6
7
O
I/O
I/O
I/O
I/O
I
LOW
I/O
DQ11
DQ12
DQ13
DQ14
DQ15
CE2
VS1
3
4
I/O
I/O
Data bit 4
Data bit 5
Data bit 12
Data bit 13
Data bit 14
Data bit 15
5
6DQ
7
8
9
I/O
I/O
I
Data bit 6
Data bit 7
CE1
A10
OE
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Oeady/BusRy
Supply Voltage
Progꢀ Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
LOW
LOW
I
O
Card Enable 2
Voltage Sense 1
Reserved
LOW
NC (2)
I
I
RFU
RFU
17
10
11
A11
I
I
Reserved
A9
I
I
I
I
I
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Progꢀ Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26A
27
28
29
30
31
32
33
34
Notes:
A8
I
I
I
A18
A13
A14
WE
A19
A20
I
LOW
LOW (4)
A21
RDY/BSY
VCC
VCC
VPP1
A16
A15
A12
A7
VPP2
A22
NC
NC
I
I
I
I
A23
I
I
A24
25
I
O
I
I
I
I
VS2
NC
HIGH
Low (3)
A6
RST
Wait
RFU
REG
BVD2
BVD1
A5
O
Extended Bus cycle
Reserved
A4
I
I
I
3
I
O
O
Attrib Mem Select
Batꢀ Voltꢀ Detect 2
Batꢀ Voltꢀ Detect 1
Data bit 8
A2
(3)
(3)
A1
I
A0
I
4
5
8
DQ I/O
DQ I/O
O
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
O
6
9
Data bit 9
Data bit 1
66
6
DQ10
Data bit 10
Card Detect 2
Ground
Data bit 2
Write Potect
Ground
7
2
CD O
LOW
HIGH
68
GND
1ꢀ RDY/BSY signal is an Open drain type output, pull-up resistor on host side is requiredꢀ
2ꢀ Wait, BVD1 and BVD2 are driven high for compatibilityꢀ
3ꢀ Shows density for which specified address bit is MSBꢀ Higher order address bits are no connects (ie: 4MB A21 is MSB A22-A25 are NC)ꢀ
4ꢀ NC - No Connection for FLV51-FLV58
Interconnect area
MECHANICAL
1.6mm 0.05
(0.063”)
3.0mm MIN
10.0mm MIN
(0.400”)
1.0mm 0.05
(0.039”)
54.0mm 0.10
(2.126”)
Substrate area
85.6mm 0.20
(3.370”)
1.0mm 0.05
(0.039”)
10.0mm MIN
(0.400”)
3.3mm T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
3
White Electronic Designs Corporation (508) 485-4000 wwwꢀwhiteedcꢀcom
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
