TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
4.5 V dc ≤ VCC ≤ 5.5 V dc,
Group A
subgroups
Device
types
Limits
Unit
Min
Max
VSS = 0 V
Unless otherwise specified
Write cycle AC timing characteristics - Continued.
Data valid to end of
write
tDW
See figure 5
9, 10, 11
9, 10, 11
01
02
03
04
20
15
12
10
ns
Write pulse width
tWP
See figure 5
01
02
03
04
25
20
17
14
ns
Address setup time
Address hold time
tAS
tAH
See figure 5
See figure 5
9, 10, 11
9, 10, 11
All
All
0
2
ns
ns
Output active from end
of write
tOW
See figure 5
See figure 5
9, 10, 11
9, 10, 11
All
0
ns
ns
Write enable to output
tWHZ
01
02
03
04
15
10
10
9
in high Z
3/
Data hold time
tDH
tBW
See figure 5
See figure 5
9, 10, 11
9, 10, 11
All
0
ns
ns
LB, UB, valid to end of
write
01
02
03
04
25
20
17
14
1/ Unless otherwise specified, the DC test conditions are as follows:
Input pulse levels; VIH = VCC - 0.3 V and VIL = 0.3 V.
Unless otherwise specified, the AC test conditions are as follows:
Input pulse levels; VIH = 3.0 V and VIL = 0.0 V.
Input rise and fall times; 5 ns.
Input to output timing reference levels; 1.5 V.
2/ Due to the nature of the 4 transistor design of the die used in these device types, topologically pure testing is important,
particularly for high reliability applications. The device manufacturer should be consulted concerning their testing
methods and algorithms.
3/ Parameters shall be tested as part of device characterization and after design and process changes. Parameters
shall be guaranteed to the limits specified in table I for all lots not specifically tested.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-96902
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
F
8
DSCC FORM 2234
APR 97
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
