SCR1100-D02
At the end of the data word the SPI master and the SPI slave have to add an additional parity bit.
Both devices have to check the received parity according to the selected parity mode odd or even.
4.2 ASIC Addressing Space
4.2.1 Register Definition
The ASIC has multiple register and EEPROM blocks. The EEPROM blocks holding the calibration
data will be programmed via SPI during manufacturing process. User only needs to access the
Data Register Block at addresses 00h and 07h - 0Ah (addresses 01h-06h are reserved). The
content of this register block is described below.
4.2.2 Data Register Block
Table 6. Register map of data register block.
Address
Register Name
Number of
Read/
Write/
Factory
Data Format Description
Dec (hex)
[bit definition]
Bits
00(00)
Rate_X[0]
1
R
-
odd Parity bit of Rate_X[14,1]
S_OK =0 Rate_X failed
S_OK =1 Rate_X valid (ok)
S_OK is generated out of the monitoring flags in the
status register (08h).
If either one of the flags in register 08h [15:2] is 0,
S_OK will be 0. Only if all flags in register 08h[15:2]
are 1 S_OK is set to 1
Rate_X[1]
00(00)
(S_OK Flag)
1
R
-
00(00)
07(07)
Rate_X[15:2]
14
13
R
F
S
-
Sensor output data format two's complement
Reserved
IC Identification
[14, 11:4, 2, 1]
IC Identification []
07(07)
07(07)
07(07)
1
1
1
r
Soft Reset bit
Writing '1' to this register bit will reset the device
Setting this bit to ‘1’ is enabling the Parity functionality
IC Identification[12]
HWParEn
W
W
This bit is selecting an even or an odd parity mode.
Bit = 0: Even Parity mode means that the number of
ones in the data word including the parity bit is even.
IC Identification[13]
HWParSel
Bit = 1: Odd Parity mode means that the number of
ones in the data word including the parity bit is odd.
Reserved
08(08)
08(08)
Status/Config
[14:10, 8:1]
14
1
F
-
-
This bit is set as soon as the SPI logic is detecting a
wrong parity bit received from the µC. This bit is
automatically cleared during read access to this
register.
Status/Config[9]
(Parity_OK)
R
Bit = 0 : Parity error
Bit = 1 : Parity check ok.
Reserved
09(09)
10(0A)
Reserved
Temp[0]
14
1
F
-
-
R
odd Parity bit of TEMP[14,1]
S_OK =0 Rate_X failed
S_OK =1 Rate_X valid
10(0A)
10(0A)
Temp[1] (S_OK Flag)
Temp[15,2]
1
R
R
-
14
S
Temperature sensor output
The offset of temperature data is factory calibrated but sensitivity of the temperature data varies
from part to part. Note: Registers marked with F are reserved for factory use only and not to be
written to.
VTI Technologies Oy
www.vti.fi
Subject to changes
11/21
Doc.Nr. 82 1130 00 A
Rev. 1.0
VTI [ VTI TECHNOLOGIES ]
