SCR1100-D02
Register Result:
D15
D14
D13
D12
D11
D10
reg9
D9
D8
D7
D6
D5
D4
D3
D2
D1
reg0
D0
reg 14
reg 13
reg 12
reg11
reg 10
reg8
reg7
reg6
reg5
reg4
reg3
reg2
reg1
par
odd
reg[14:0] :
par odd :
value of the internal register. All bits, which are not used, are set to zero.
see Address Transfer
Figure 6 shows an example of communication sequence:
Figure 5. Communication example.
Each communication frame in the figure 6 contain 16 SCK cycles. After communication start
(CSN_G falling edge) the master sends ADR1 and performs a read access. In parallel the slave
sends Status Flags. During the transmission of the next data word (ADR2) the slave sends the
register value of ADR1 (Result_1). On ADR2 the master performs a write access (RW='1'). The
slave stores Data_2 in the register of ADR2 and sends the current register value of ADR2 to
MISO_G. After the transmission of data value during a write access the slave always sends Status
Flags. To receive Result_5 of the last read access the Master has to send an additional word ('Zero
Vector').
4.1.2 SPI Transfer Parity Mode
SCR1100 gyro ASIC is able to support parity check during SPI Transfer. This functionality is
controlled by the IC Identification Register. The internal parity status is reported in Status/Config
Register.
With parity enable bit set the SCR1100 gyro ASIC is expecting an additional parity bit after the
transmission of each 16 bit data word. This additional parity bit requires an additional SCK cycle,
i.e. the SPI frame consists of 17 SCK cycles instead of the normal 16 SCK cycles. Detecting a
wrong parity bit has the following consequences:
During read access:
The Parity Error Flag in the Status/Config Register is set. The SCR1100 reports the contents of the
received register address.
During write access:
The Parity Error Flag in the Status/Config Register is set. The SPI Write Access is cancelled.
These actions are performed either if the parity failure is detected in the address word or the data
word.
Due to the additional parity bit a single SPI Transfer is using now 17 Bit as shown in the Figure 7.
Figure 6. Communication in parity mode.
VTI Technologies Oy
www.vti.fi
Subject to changes
10/21
Rev. 1.0
Doc.Nr. 82 1130 00 A
VTI [ VTI TECHNOLOGIES ]
