SCA61T Series
2.4 SPI Serial Interface
A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave
devices. The master is defined as a micro controller providing the SPI clock and the slave as any
integrated circuit receiving the SPI clock from the master. The ASIC in VTI Technologies’ products
always operates as a slave device in master-slave operation mode.
The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a low
active Slave Select or Chip Select wire (CSB). Data is transmitted with a 3-wire interface consisting
of wires for serial data input (MOSI), serial data output (MISO) and serial clock (SCK).
MASTER
MICROCONTROLLER
SLAVE
SI
DATA OUT (MOSI)
DATA IN (MISO)
SO
SERIAL CLOCK (SCK)
SCK
SS0
SS1
CS
SI
SS2
SS3
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
Figure 9.
Typical SPI connection
The SPI interface in VTI products is designed to support any micro controller that uses an SPI bus.
Communication can be carried out by a software or hardware based SPI. Please note that in the
case of a hardware based SPI, the received acceleration data is 11 bits. The data transfer uses
the following 4-wire interface:
MOSI
MISO
SCK
master out slave in
master in slave out
serial clock
µP → SCA61T
SCA61T → µP
µP → SCA61T
µP → SCA61T
CSB
chip select (low active)
Each transmission starts with a falling edge of CSB and ends with the rising edge. During
transmission, commands and data are controlled by SCK and CSB according to the following
rules:
•
•
•
•
commands and data are shifted; MSB first, LSB last
each output data/status bits are shifted out on the falling edge of SCK (MISO line)
each bit is sampled on the rising edge of SCK (MOSI line)
after the device is selected with the falling edge of CSB, an 8-bit command is received. The
command defines the operations to be performed
•
•
the rising edge of CSB ends all data transfer and resets internal counter and command register
if an invalid command is received, no data is shifted into the chip and the MISO remains in
high impedance state until the falling edge of CSB. This reinitializes the serial communication.
data transfer to MOSI continues immediately after receiving the command in all cases where
data is to be written to SCA61T’s internal registers
•
VTI Technologies Oy
www.vti.fi
Subject to changes
Doc. nr. 8261900
10/18
Rev.A
VTI [ VTI TECHNOLOGIES ]
