SCA3000 Series
2.5 Ring Buffer
2.5.1 Description
The SCA3000's Ring Buffer is a 192 acceleration data samples long (64 samples of 11 bit three
axis data) internal memory to relax the real-time operation requirements of the host processor. The
following parameters are configurable:
1. Each measurement axis can be individually disabled. If measurement data from e.g. Y-axis
is not needed, available memory can be used for X- and Z-axis data.
2. Buffer data length can be changed from 11 to 8 bits. In 8-bit mode, data can be read out
using shorter read sequence.
3. Ring buffer's input sample rate can be the same as the sensor's data rate or divided by 2
or 4. When the divider is e.g. 2, only every 2nd acceleration data will be stored.
4. The Interrupt condition, when enabled, can be selected between two: interrupt in INT-pin
occurs when the buffer is 50% or 75% full.
2.5.2 Usage
The ring buffer can be enabled by setting BUF_EN bit in MODE register to "1". After enabling the
buffer, acceleration data can be read from BUF_DATA register using decrement register read,
which is described in section 4.1.3.2 for SPI and 4.2.1.3 for I2C interface.
Each measurement axis can be individually disabled by setting corresponding bits in BUF_X_EN,
BUF_Y_EN and BUF_Z_EN in OUT_CTRL register to "0".
Output data length can be changed from 11 bits to 8 bits by setting bit BUF_8BIT in MODE register
to "1". See section 3.3 for bit level descriptions.
The count of available data samples in output ring buffer can be read from BUF_COUNT register.
Register value is updated only when it is accessed over the SPI or I2C.
Data shift out order is X,Y,Z. In 11 bit mode two bytes must be read to get all 11 bits out. In that
case, the MSB byte is 1st. Examples:
1. 11 bits data length, X&Y&Z axis enabled:
X1_MSB, X1_LSB, Y1_MSB, Y1_LSB, Z1_MSB, Z1_LSB, X2_MSB, X2_LSB, ... latest
Z_LSB
2. 11 bits data length, Y&Z axis enabled:
Y1_MSB, Y1_LSB, Z1_MSB, Z1_LSB, Y2_MSB, Y2_LSB, Z2_MSB, Z2_LSB, Y3_MSB,
Y3_LSB, ..., latest Z_LSB
3. 8 bits data length, all axis enabled:
X1, Y1, Z1, X2, Y2, Z2,..., latest Z
4. 8 bits data length, X&Z axis enabled:
X1, Z1, X2, Z2, X3, Z3, ..., latest Z
5. 8 bits data length, Z axis enabled:
Z1, Z2, Z3, ... , latest Z
See section 2.7 for interrupt functionality details.
Acceleration data is available in X_LSB, X_MSB, Y_LSB, Y_MSB, Z_LSB and Z_MSB when the
ring buffer is enabled.
2.5.2.1 Overflow condition
Overflow is detected from data ring buffer in same way as from the output registers. See section
2.2.2.1 for details.
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Doc.Nr. 8257300A.06
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