CMA3000-D0X Series
4
Serial Interfaces
Communication between the CMA3000 sensor and master controller is based on serial data
transfer and a dedicated interrupt line (INT-pin). Two different serial interfaces are available for the
CMA3000 sensor: SPI and I2C (Phillips specification V2.1). Selection between these two interfaces
is done using the chip select signal. The I2C interface can be also disabled by re-configuring
register content. The CMA3000 acts as a slave on both the SPI and I2C bus.
4.1 SPI Interface
SPI bus is a full duplex synchronous 4-wire serial interface. It consists of one master device and
one or more slave devices. The master is defined as a micro controller providing the SPI clock, and
the slave as any integrated circuit receiving the SPI clock from the master. The CMA3000 sensor
always operates as a slave device in master-slave operation mode. A typical SPI connection is
presented in Figure 6.
MASTER
MICROCONTROLLER
SLAVE
SI
DATA OUT (MOSI)
DATA IN (MISO)
SO
SERIAL CLOCK (SCK)
SCK
SS0
SS1
CS
SI
SS2
SS3
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
Figure 6. Typical SPI connection
The data transfer uses the following 4-wire interface:
MOSI
MISO
SCK
master out slave in
master in slave out
serial clock
µC → CMA3000
CMA3000 → µC
µC → CMA3000
µC → CMA3000
CSB
chip select (low active)
4.1.1 SPI frame format
CMA3000 SPI frame format and transfer protocol is presented in Figure 7.
CSB
SCK
MOSI
MISO
1
2
3
4
5
6
7
8
9
10
DI6
DO6
11
DI5
DO5
12
DI4
DO4 DO3
13
14
DI2
DO2
15
DI1
DO1
16
DI0
DO0
A5
A3
A0
DI7
DO7
DI3
A4
A2
PORST
A1
RB/W
Figure 7. SPI frame format
Each communication frame contains 16 bits. The first 8 bits in MOSI line contains info about the
register address being accessed and the operation (read/write). The first 6 bits define the 6 bit
address for the selected operation, which is defined by bit 7 (‘0’ = read ‘1’ = write), which is
followed by one zero bit. The later 8 bits in the MOSI line contain data for a write operation and are
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