Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 4. Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High level
is required
CKE
Minimum of 8 Refresh cycles are required
2 Clock min.
CS
RAS
CAS
WE
DSF
BS
A9
Address Key
A0 ~ A8
DQM
DQ
t
t
RC
RP
Hi-Z
2nd Auto Refresh
Command
Mode Register
Set Command
Any
Command
Precharge All
Command
1st Auto Refresh
Command
Inputs must be
stable for 200 us
Document:
Rev.1
Page4