Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
-5 Version (Calculation with t = 5ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RCD
RC
RP
RRD
RAS
RSC
)
CK
55ns
15ns
10ns
40ns
10ns
15ns
30ns
20ns
15ns
10ns
5ns
2
3
1
1
1
2
3
1
1
1
1
2
2
2
3
4
8
1
1
1
1
2
1
1
1
2
3
4
6
11
-5.5 Version (Calculation with t = 5.5ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RCD
RC
RP
RRD
RAS
RSC
)
CK
56.5ns
16.5ns
11ns
40ns
11ns
16.5ns
30ns
20ns
15ns
10ns
5.5ns
2
3
1
1
2
2
3
1
1
1
2
2
2
2
3
4
8
1
1
1
2
2
1
1
2
2
3
4
6
11
-6 Version (Calculation with t = 6ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RCD
RC
RP
RRD
RAS
RSC
)
CK
60ns
18ns
12ns
42ns
12ns
18ns
30ns
20ns
15ns
10ns
6ns
2
3
1
1
2
2
3
1
1
1
2
2
2
3
3
5
7
1
1
1
2
2
1
1
2
2
3
4
6
10
-7 Version (Calculation with t = 7ns ~ 30ns)
CK
Clock period
(t
t
t
t
t
t
t
RCD
RC
RP
RRD
RAS
RSC
)
CK
62ns
20ns
14ns
42ns
14ns
20ns
30ns
20ns
15ns
10ns
7ns
3
4
1
1
2
2
3
1
1
1
2
2
2
3
3
5
6
1
1
1
2
2
1
1
2
2
3
5
7
10
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V and V (simultaneously) when all input signals are held “NOP”
DD
DDQ
state and CKE = ”H”, DQM = ”H”. The CLK signal must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that
DQM is held “high” (V levels) to ensure DQ output to be in the high impedance.
DD
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device. Sequence of 4 and 5 may be changed.
Document:
Rev.1
Page25
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
