Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Recommended D.C. Operating Conditions (V = 3.3V ± 0.3V, Ta = 0 ~ 70°C)
DD
-4.5
Min. Max. Min. Max. Min. Max Min. Max. Min. Max.
-5
-5.5
-6
-7
Unit Note
Description/test condition
Symbol
Operating Current
³ t , Outputs Open
I
230
220
210
200
180
3,4
DD1
t
RC
RC(min )
Address changed once during t
.
CK(min)
Burst Length = 1, One bank active
Precharge Standby Current in non power-down
mode
I
45
20
45
20
45
20
45
20
45
20
3
DD2N
t
= 15ns, CS ³ V
, CKE ³ V
(min)
IH
CK
(min)
IH
Input signals are changed once during 30ns.
Precharge Standby Current in non power-down
mode
I
DD2NS
mA
t
= ¥ , CKE ³ VIH
, CLK £ V
(min)
IL
CK
(max)
Input signals are stable
Precharge Standby Current in power-down
mode
I
2
2
2
2
2
2
2
2
2
2
3
DD2P
t
=15ns, CKE £ V
IL
CK
(max)
Precharge Standby Current in power-down
mode
I
DD2PS
t
= ¥ , CKE £ V
, CLK £ V
(max)
IL
CK
(max)
IL
Active Standby Current in non power down
mode
I
50
50
50
50
50
3
DD3N
DD3P
CKE ³ VIH
, t = 15ns(Both Bank Active)
(min) CK
Input signals are changed once during 30ns.
Active Standby Current in power-down mode
I
5
5
5
5
5
CKE £ VIL
CS ³ V
, t
15ns,
(max) CK =
(Both Bank Active)
IH(min)
Operating Current (Page Burst, and All Bank
activated)
I
I
310
290
275
260
230
4,5
3
DD4
DD5
t
= t
, Outputs Open,
CCD
CCD(min)
Multi-bank interleave, gapless data
Refresh Current
230
220
210
200
180
tRC ³ tRC
(t
= 32ms)
(min) REF
Self Refresh Current
I
I
3.5
3.5
3.5
3.5
3.5
DD6
DD7
CKE £ 0.2V
Operating Current (One Bank Block Write)
230
210
200
180
150
t
= t
, Outputs Open, t
= t
CK
CK(min)
BWC BWC(min)
Parameter
Description
Input Leakage Current
Min.
Max.
Unit
Note
I
-5
5
mA
IL
(0V £ V £ V
All other pins not under test = 0V)
IN
DD
I
Output Leakage Current
-5
5
mA
OL
Output disable, (0V £ V
£ V
)
OUT
LVTTL Output ”H” Level Voltage
(l = -2mA)
DDQ
V
2.4
-
V
OH
OUT
Document:
Rev.1
Page21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
