VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Figure 15.1. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
CS
RAS
CAS
WE
DSF
BS
RAx
RAx
RBw
RBw
A9
A0 ~ A8
CAy
CAx
CBx
CBz
CBy
CBw
tRP
tWR tRP
t
RCD
DQM
DQ
t
RRD
Hi-Z
DBy1
DBy0
DBz2
DBz1
DBx1
DAy0
Write
DBz0
Write
DBz3
DBw0
Write
DAy1
DAx3
DBx0
Write
DAx2
DBw1
DAx1
DAx0
Precharge
Command
Bank B
Activate
Activate
Command
Bank A
Write
Command
Bank B
Command
Bank A
Command
Command
Command
Bank B
Command
Bank B
Bank B
Bank B
Precharge
Write
Command
Bank A
Command
Bank A
Document:1G5-0145
Rev.1
Page57
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
