VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Interleaving Column Read Cycle
Figure 14.2
(Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
DSF
BS
RBw
RBw
RAx
RAx
A9
A0 ~ A8
CBz
CBw
CBx
CBy
CAy
CAx
t RCD
tAC2
DQM
DQ
Hi-Z
Ax0
Ay0
Bz1
Ax1 Ax2 Ax3 Bw0 Bw1
Ay1
Bz3
Bx0 Bx1
Read
By1
Bz0
Bz2
By0
Precharge
Command
Bank B
Activate
Command Command
Read
Read
Activate
Read
Read
Read
Command
Bank B
Command
Command
Bank B
Command
Bank B
Command
Command
Bank A
Bank A
Bank B
Bank B
Bank A
Precharge
Command
Bank A
Document:1G5-0145
Rev.1
Page55