Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Random Column Write (Page Within same Bank) (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
BS
Ra
Ra
Rd
Rd
A10
Cb
Cc
Ca
Cd
ADD
DQM
Hi-Z
Da0
Dc2 Dc3
Dd2 Dd3
Da1 Da2
Db0 Db1 Dc0
Dd0
Da3
Dc1
Dd1
DQ
Precharge
Command
Bank B
Write
Command
Bank B
(Bank D)
Activate
Command
Bank B
Write
Command
Bank B
(Bank D)
Activate
Command
Bank B
Write
Command
Bank B
(Bank D)
Write
Command
Bank B
(Bank D)
(Bank D)
(Bank D) (Bank D)
Document : 1G5-0153
Rev.1
Page44