Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Self Refresh (Entry and Exit)
CLK can be Stopped
*
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
t
SRX
SRX
t
CKS
t
CKS
CS
RAS
CAS
WE
BS
A10
ADD
DQM
t
t
RC
RC
Hi-Z
DQ
All Banks
must be idle
Self refresh
Entry
Self Refresh
Exit
Self Refresh
Entry
Activate
Command
Self Refresh
Exit
* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
Document : 1G5-0153
Rev.1
Page41