Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
Clock Suspension During Burst Read (Using CKE) (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
CS
RAS
CAS
WE
BS
RAa
A10
CAa
RAa
ADD
DQM
t
HZ
Hi-Z
QAa1
QAa0
QAa2
QAa3
DQ
Clock
Suspended
1 Cycles
Clock
Suspended
2 Cycles
Clock
Suspended
3 Cycles
Read
Command
Bank A
Activate
Command
Bank A
Document : 1G5-0127
Rev2
Page36