VG36256401A
VG36256801A
Preliminary
VG36256161A
CMOS Synchronous Dynamic RAM
VIS
(2/3)
Current state CS RAS CA WE
Address
Command
Action
Notes
Read with auto
precharge
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
BST
Continue burst to end ® Prcharging
Continue burst to end ® Prcharging
Illegal for single bank, but illegal for
multibanks interleave
L
H
L
H
BA, CA, A10 READ/READA Illegal for single bank, but illegal for
multibanks interleave
L
H
L
L
BA, CA, A10 WRIT/WRITA ILLEGAL
L
L
L
L
H
L
L
L
L
X
H
H
L
H
L
BA, RA
BA, A10
X
ACT
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
3
3
PRE/PALL
PEF/SELF
MRS
H
L
L
Op - Code
X
Write with auto
precharge
X
X
DESL
Continue burst to end® Write
recovering with auto precharge
L
H
H
H
X
X
NOP
BST
Continue burst to end® Write
recovering with auto precharge
ILLEGAL
L
L
H
H
H
L
L
H
BA, CA, A10 READ/READA Illegal for single bank, but legal for
multibanks interleave
L
H
L
L
BA, CA, A10 WRIT/WRITA Illegal for single bank, but legal for
multibanks interleave
L
L
L
L
H
L
L
L
L
X
H
H
L
H
L
BA, RA
BA, A10
X
ACT
ILLEGAL
3
3
PRE/PALL
PEF/SELF
MRS
ILLEGAL
H
L
ILLEGAL
L
Op - Code
X
ILLEGAL
precharging
X
X
DESL
Nop ® Enter idle after tRP
L
L
H
H
H
H
H
L
X
X
NOP
BST
Nop ® Enter idle after tRP
Nop ® Enter idle after tRP
L
L
L
L
H
H
L
L
L
H
L
BA, CA, A10 READ/READA ILLEGAL
BA, CA, A10 WRIT/WRITA ILLEGAL
3
3
3
H
H
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
Nop ® Enter idle after tRP
L
L
L
L
X
L
L
X
H
L
X
PEF/SELF
MRS
ILLEGAL
Op - Code
X
ILLEGAL
Row activating
H
X
DESL
Nop ® Enter row active idle after tRCD
L
L
H
H
H
H
H
L
X
X
NOP
BST
Nop ® Enter row active idle after tRCD
Nop ® Enter row active idle after tRCD
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
BA, CA, A10 READ/READA ILLEGAL
BA, CA, A10 WRIT/WRITA ILLEGAL
3
3
H
H
L
H
L
BA, RA
BA, A10
X
ACT
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
3,9
3
PRE/PALL
PEF/SELF
MRS
H
L
L
Op - Code
Document : 1G5-0155
Rev.1
Page 11
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
