Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
Precharge Termination of a Burst (1 of 2)
Burst Length=4,8 or Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
RAa
RAb
RAb
RAc
RAc
A10
A0~A9
RAa
CAa
CAb
CAc
t
t
t
t
RP
RP
DPL RP
DQM
DQ
Hi-Z
QAb1
QAa0
QAb0
QAc2
QAa1 QAa2
QAb2
QAc1
QAc0
Da3
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Read
Command
Bank A
Read
Command
Bank A
Precharge
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Command Command
Bank A
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Precharge Termination
of a Read Burst.
Document:1G5-0160
Rev.1
Page 68
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
