Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
RAa
RBb
A10
RBa
A0~A9
CAa
RBb
RAa
CBa
RBa
DQM
DQ
t
BDL
Hi-Z
DAa+1
DBa+1
Write
Command
Bank B
DAa
DBa
DBa+2
DBa+4
DBa+6
DBa+5
DAa DAa+1
DAa-1
DBa+3
DAa+2 DAa+3
Data is ignored
Write
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Command
Bank A
Full page burst operation
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Document:1G5-0160
Rev.1
Page 62
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
