VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC838
I/O Equivalent Circuits
ITC
VCC
3.2Gb/s
36x37 Crosspoint Switch
TERM_CTRL
50
PAD
50
PAD
PAD
50
50
PAD
DRIVE_CTRL
H/S Input Equivalent Circuit
H/S Output Equivalent Circuit
Input Termination
The high-speed inputs of the VSC838 are internally terminated by a 100
Ω
impedance between true and
complement inputs. Termination resistors are isolated from each other on-chip. The termination will self-bias to
+2.0V (nominal) for AC-coupled applications. The ITC pin enables direct interconnection of multiple VSC838
devices. With ITC tied to V
CC
, the center point of the 100
Ω
termination impedance is tied to V
CC
, causing the
terminations to act as loads for an open-drain or open-collector differential output.
Table 7: Allowed Input Termination Schemes
Type
1
2
3
4
5
Description
AC-coupled input
DC-coupled from open-drain CML
DC-coupled from back-terminated 2.5V CML
DC-coupled from back-terminated 2.5V CML
DC-coupled from back-terminated 3.3V LV-PECL
Comments
Tie ITC LOW, 100Ω differential input termination,
input self-biased
Tie ITC HIGH, terminations acts as 50Ω load to V
CC
Tie ITC HIGH, terminations acts as 50Ω load to V
CC
Tie ITC LOW, 100Ω differential termination
(preferred over Type 3)
Tie ITC LOW, 100Ω differential termination
Some allowed termination schemes result in additional I
CC
current and power dissipation on-chip. See
Table 8.
Table 8: Additional Current and Power
Parameter
I
CC-C
P
CC-C
Description
Additional ICC current when receiving DC-
Coupled CML (ITC = HIGH)
Min
Typ
Max
180
0.180
Units
mA
W
Conditions
Additional power dissipated on-chip for
DC terminating CML at inputs
G52351-0, Rev 3.0
02/12/01
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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