VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC838
3.2Gb/s
36x37 Crosspoint Switch
Figure 3: Serial Mode (leave ALE_SCN pin LOW during programming)
INCHAN0_SDIN
INCHAN1_SCLK
Y5
Y4
Y3
Y2
low
Y1
Y0
A5
A4
A3
A2
low
A1
A0
T
dSDOUT
SDOUT
LOAD
CS
CONFIG
SERIAL
T
sSERIAL
Y(n) = Output Address Bit (n); A(n) = Input Address Bit (n)
Y5
Y4
Y3
Y2
T
sSDIN
T
hSDIN
T
sCS
T
perSCLK
T
sLOAD
T
hLOAD
T
PWCFG
T
hCS
Figure 4: Serial Read-Back
ALE_SCN
INCHAN1_SCLK
SDOUT
SERIAL
T
sSERIAL
T
hSCAN
T
sSCAN
T
dSDOUT
T
perSCLK
36
b5
36
b4
36
b3
36
b2
36
low
36
b1
36
b0
35
b5
35
b4
35
b3
35
b2
35
low
35
b1
35
b0
34
b5
MSB of Program memory for
Activity Monitor Channel
MSB of Program memory for 36
th
output channel
Read-back shift register (483 bits long) is loaded here
on rising edge of INCHAN1_SCLK with SERIAL HIGH
and ALE_SCN LOW
NOTE: The word pattern during serial read back will be four valid words followed by four ‘DON’T CARE’ words.
G52351-0, Rev 3.0
02/12/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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