VITESSE
SEMICONDUCTOR CORPORATION
2.5 Gbits/sec
34x34 Crosspoint Switch with Signal Detection
Datasheet
VSC835
Table 4: Programming Port Interface Timing
Parameter
T
config
T
pdADDR
T
pdRDB
T
pdint
T
pdstate
T
sRDB
T
hRDB
T
sWRB
T
hWRB
T
sCONFIG
T
sCSB
T
pwCONFIG
T
pwWRB
T
pwRDB
T
tsDATA
Switch configuration delay
Data read propagation delay from ADDR
Data read propagation delay from RDB (1)
Interrupt propagation delay from MONCLK (2)
MONCLK to internal state register change delay (2)
ADDR to RDB setup time
RDB to ADDR hold time
WRB setup time (for either ADDR or DATA)
WRB hold time (for either ADDR or DATA)
WRB to CONFIG setup time
CSB setup time (to either WRB or RDB)
CONFIG pulse width (high)
WRB pulse width (low and high)
RDB pulse width (low and high)
DATA tri-state delay (from either RDB or CSB) (2)
Description
Min
-
-
-
-
-
5
3
5
3
1
0
10
10
10
-
Max
6
30
7
50
6
-
-
-
-
-
-
-
-
-
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
note 1: measured from falling edge.
note 2: measured from rising edge.
DC Characteristics
(over the specified operating conditions)
Table 5: Power
Parameter
I
CC
P
T
I
TERM-V
I
TERM-E
V
CC
supply current
Total chip power
V
TERM
supply current with V
TERM
=V
CC
-1.3V
V
TERM
supply current with V
TERM
=V
CC
-2.0V
Description
(Max)
4060
14
~0
-950
Units
mA
W
mA
mA
Note: Icc Specified with outputs terminated with 50 ohms to +2.0V and Chip Vterm=+2.0V, Vcc = 3.45V
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52270-0, Rev. 4.1
7/24/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
