VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.5 Gbits/sec
34x34 Crosspoint Switch with Signal Detection
VSC835
Programming Interface
The switch core is programmed through a parallel interface circuit that allows random reads or writes to the
program memory array. The program memory array is buffered to allow multiple programming instructions to
be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate and
state read-back can be performed at up to 25MHz.
The program data is composed of two parts: output address and input address. The output address, denoted
by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[5:0],
specifies which input port the switch slice should connect to. The format of the program data is simple binary.
For example: ADDR[5:0] (000100) / DATA[5:0] (000110) would direct output channel Y4 to connect to input
channel A6. The programming state may be verified (read back) by applying the address of the desired output
and asserting RDB. The programming state is unknown at power-on. Additional address space is provided for
access to the monitor registers (see sections below). The microprocessor interface consists of the following sig-
nals. Levels are TTL (see DC Characteristics)
:
Table 1: Programming Interface Signal Table
Pin
I/O
Description
D[5:0]
A[5:0]
ALE
B
I
Bidirectional data bus to transfer data to/from internal program registers
Address bus to select internal program registers for read-write operations
ALE functionality is not implemented at this time. Tie this pin High.
I
CSB
I
Chip Select (Active Low): assert this pin whenever the part is being read or programmed.
Write (Active Low): program data will be transferred to the first level internal registers on the rising
edge of this signal (when CSB is also low).
WRB
I
Read (Active Low): program data from the internal program or monitor registers will be read out on the
data bus when this signal goes low (with CSB also low).
RDB
I
INTB
O
Interrupt (Active Low): this signal is asserted when an LOA condition is found
Configure (Active High): assert this signal to transfer queued program information from the first-level
internal registers to the second-level registers, making the programming take effect. This signal may be
tied high to leave the second-level registers transparent so all programming will take effect
immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a high-
order bit of the address bus
CONFIG
I
I
Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not
expected to exceed 3MHz.
MONCLK
Loss of Activity (LOA) Monitoring
The LOA function consists of an activity monitor on each input channel, connected directly to the pads.
The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying
1
the address of the monitor register corresponding to the signal of interest and asserting RDB. Each monitor
rd
register is four bits in length, covering the state of four inputs. There is one extra two-bit monitor for the 33
th
and 34 inputs. The state of each monitor is transferred to the register on the rising edge of MONCLK, where-
upon the activity monitor is cleared until more activity is detected.
1. See Memory Map Table
G52270-0, Rev. 4.1
7/24/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
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