VSC8201DL
Special RGMII Implementation Using a Single 3.3V Supply
This section addresses designers who wish to use the VSC8201 Single Port Gigabit Ethernet PHY in RGMII interface mode at an inter-
face voltage of 3.3V, rather than the standard1 2.5V.
VSC8201’s RGMII Interface Description
The VSC8201 PHY is designed, as per the RGMII version 1.2a specification, to support RGMII operation at a 2.5v I/O supply. In addition
to the RGMII requirements specified by the standard, the PHY also has an internal clock delay feature (enabled by setting MII Register
23.8) that adds an internal delay of ~2ns to the RXC and the TXC signals when operating at 2.5v. This feature eliminates the need for
PCB trace delays or 2ns buffers in the path of the RXC and TXC traces.
Due to customer interest in using the VSC8201 PHY in RGMII interface mode with a single 3.3v supply, Vitesse has characterized the
RGMII I/O timing of the PHY under this condition in the following two configurations:
•
•
Standard RGMII Implementation (i.e. with RXC and TXC trace delays on the PCB)
RGMII Implementation using the Internal Clock Delay feature.
Since the VSC8201 PHY was not specifically designed for RGMII operation with a 3.3v I/O supply, certain accommodations must be
made to the board layout in order to ensure a robust interface. The VSC8201 PHY complies with the I/O timing requirements specified in
the RGMII version 1.2a specification. No special board layout considerations other than those mentioned in the standard are required for
this implementation.
RGMII Implementation using the Internal Clock Delay feature with 3.3v I/O Supply
With a 3.3v I/O supply, the worst case internal delay added to the TXC signal is around 3ns. If the TXC, TD[3:0], and TX_CTL traces are
length matched on the PCB, then the PHY may mis-latch data under the worst case TXC delay conditions, resulting in packet errors at
the MAC/PHY transmit interface. Due to this it is important to follow the guidelines mentioned in the section below during board layout.
1. RGMII Version 1.2a
Rev. 1.6.3 - 9/29/04
VITESSE - CONFIDENTIAL & PROPRIETARY - DO NOT COPY WITHOUT PERMISSION
- Page 11 of 21 -
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
