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VSC8151XX 参数 Datasheet PDF下载

VSC8151XX图片预览
型号: VSC8151XX
PDF下载: 下载PDF文件 查看货源
内容描述: [Terminator, 1-Func, PQFP160, 28 X 28 MM, HEAT SINK, PLASTIC, QFP-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 28 页 / 457 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
Features
• Integrated 2.488Gb/s Transceiver
• SONET/SDH Transport Overhead Output
• SONET/SDH Transport Overhead Modification
• B1 Error Detection, Re-calculation, and Insertion
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
• Support for Multiple SONET/SDH Rates
• LOF/SEF Alarm Generation
• Section & Line AIS Insertion
• 50Ω Source Terminated 2.488Gb/s I/O
General Description
The VSC8151 is a 2.488Gb/s Section Termination device which both monitors and modifies the section and
line overhead of a received SONET/SDH signal, and can generate AIS-L maintenance signals for trouble sec-
tionalization. These features allow all section termination requirements to be supported for Operations, Admin-
istration, Management, and Provisioning (OAM&P) functions in SONET/SDH terminal and optical networking
applications. An integrated 2.488Gb/s serial transceiver isolates the SONET/SDH signal interface, allowing
protocol information to be exchanged with programmable logic using a low-speed TTL interface.
VSC8151 Functional Block Diagram
LOS
FRDETEN
CONTROL
& ALARM
DETECTION
RXFRERR
RXSEF
RXLOF
RXSIN+/-
RXSCLKIN+/-
1:8
DMX
RXPIN[7:0]
FRAMING
PCLKIN
DESCRAMBLER
OVERHEAD
OUTPUT
RXFPOUT
RXOHCLK
RXOHOUT[7:0]
SYSRST
TXSCLKIN+/-
TXOHWI
TXWRENA
TXADDR[5:0]
TXOHIN[7:0]
TXFPOUT
Internal 311MHz
Clock Source
B1
MONITOR
Internal 311MHz
Clock Source
ASSEMBLER
OVERHEAD
INPUT &
INTERNAL
CONTROL
PCLKIN
AIS
GENERATION
SCRAMBLER
& B1 CALC
8:1
MUX
TXSCLKOUT+/-
TXSOUT+/-
Functional Overview
The VSC8151 is divided into two logic sections, a monitoring section and a modification section, each
interfaced externally through both 2.5Gb/s serial interfaces as well as 16-bit parallel interfaces. Incoming
SONET/SDH data is demultiplexed, framed, descrambled, and the 27 bytes of the section and line overhead are
output. The BIP parity of the incoming signal is calculated and compared with the received B1 and B2 bytes for
calculating received parity errors. The byte aligned data, calculated B1/B2 parity, and frame boundary location
G52225-0, Rev. 2.3
8/16/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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