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VSC8151XX 参数 Datasheet PDF下载

VSC8151XX图片预览
型号: VSC8151XX
PDF下载: 下载PDF文件 查看货源
内容描述: [Terminator, 1-Func, PQFP160, 28 X 28 MM, HEAT SINK, PLASTIC, QFP-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 28 页 / 457 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Figure 5: Functional Block Diagram of Frame Acquisition Circuit
FRD
SL1
SL0
RXFRERR
RXSEF
RXLOF
RXFPOUT
FRAME SYNC.
COUNTER
RESYNC
BYTE
ALIGN
Aligned Output
ERROR/ALARM
DETECTION
RXSIN
1:8
DMX
FRAME
DET
The frame boundary detection/verification is based on 12, 24 or 48 bits of the A1/A2 overhead (See
Figure 6) depending on the setting of the FRDET register (See Table 1). Frame acquisition procedures are con-
trolled by the settings of the FRDET register. Reframing can be controlled manually or reframing can automati-
cally be initiated by the presence of an SEF signal. Using SEF is an indicator that reframe is necessary will
achieve realignment within 250uS or the receipt of two error free framing patterns (R5-225)
A frame detect based on 24 bits will result in an SEF alarm at an average of no more than once every 6 min-
utes assuming a BER of 10-3 (R5-224). A frame detect based on 48 bits or 12 bits will result in a mean time
between SEF detects of 0.43 minutes and 103 minutes respectively.
Figure 6: Frame Detection Patterns
48 bits
24 bits
12 bits
A1 (0xF6)
A1 (0xF6)
A1 (0xF6)
A2 (0x28)
A2 (0x28)
A2 (0x28)
Loss of Signal
The LOS (Loss of Signal, active high) input should be asserted whenever the interfacing module no longer
generates a valid electrical signal on the high speed clock and/or data lines of the VSC8151. If the clock signal
is present when the LOS input is asserted the VSC8151 will assert SEF and other outputs will become invalid. If
the input clock is not present, then the transition of the LOS input will not be detected and the part is effectively
frozen. Asserting LOS will force SEF (Severely Errored Frame) and LOF (Loss of Frame) high, and force all
0’s to be output from the device, regardless of the input.
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52225-0, Rev. 2.3
8/16/99