VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8132
Missed Clock
Pulse
(1)
CLK78 (Out)
(1)
2.488Gb/s 1:32 SONET/SDH Demux
Figure 4: Framing Sequence
Approximately <110µs
SYNC PULSE (Out)
OOFN (In)
(asynchronous)
Set HIGH, less than 110µs
after SYNC goes HIGH
NOTE: (1) No missing clock pulse for CLK78 when VSC8132 is working as a dumb demux.
Once frame occurs and OOFN is set HIGH, the no framing will occur until
OOFN is set LOW again. The VSC8132 will remain framed with SONET frame.
Table 1: AC Characteristics
Parameters
t
DATApd
t
CLKRpd
t
CLKFpd
t
DEDGE
t
CLKEDGE
t
CONEDGE
t
SERSU
t
SERHO
f
MAX
t
CLK38Rpd
t
CLK38Fpd
t
CLK51Rpd
t
CLK51Fpd
t
PD1
, t
PD2
Description
Data Valid From Falling Edge of 77.76MHz
High-speed Clock Rising Edge to 77.76MHz
Clock Rising Edge
High-Speed Clock Rising Edge to 77.76MHz
Clock Falling Edge
D[0:31] Edge Rate (10%-90%)
77.76, 51.84, 38.88MHz Edge Rates (10%-90%)
Control Signals (SYNC, PARITY, DTALARM,
and CKALARM) Edge Rate (10%-90%)
DI+ Setup Time with Respect to Falling Edge of
CLKI+
DI+ Hold Time with Respect to Falling Edge of
CLKI+
Demux Input Maximum Clock Frequency
High-Speed Clock Rising Edge to 38.88MHz
Clock Rising Edge.
High-Speed Clock Rising Edge to 38.88MHz
Clock Falling Edge
High-Speed Clock Rising Edge to 51.84MHz
Clock Rising Edge
High-Speed Clock Rising Edge to 51.84MHz
Clock Falling Edge
Data Invalid Window
Min
230
2.5
2.3
-
-
-
100
75
-
2.0
2.0
2.0
2.0
0, 230
Typ
Max
1250
8.0
7.1
2.0
2.0
2.0
-
-
2.9
6.3
5.9
6.0
5.9
0, 1250
Units
ps
ns
ns
ns
ns
ns
ps
ps
GHz
ns
ns
ns
ns
ps
Conditions
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
See Figure 3
See Figure 3
External load = 5pf
External load = 5pf
External load = 5pf
External load = 5pf
G52250-0, Rev 3.1
12/7/00
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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