VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8117
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Good analog design practices should be applied to the board design for these external components. Tightly
controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi-
cated PLL power (VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter genera-
tion within the clock synthesis unit. This is accomplished by either using a ferrite bead or a C-L-C choke (π
filter) on the (VDDA) power pins. Note: Vitesse recommends a (π filter) C-L-C choke over using a ferrite bead.
All ground planes should be tied together using multiple vias.
Reference Clocks
To improve jitter performance and to provide flexibility, an additional differential PECL reference clock
input is provided. This reference clock is internally XNOR’d with a TTL reference clock input to generate the
reference for the CMU. Vitesse recommends using the differential PECL input and tieing the unused TTL refer-
ence clock low. If the TTL reference clock is used the positive side of the differential PECL reference clock
“REFCLKP+” should be tied to ground. “REFCLKP+/-” are internally biased with on-chip resistors to 1.65(for
3.3V case) volts, see figure 13 for schematic of internal biasing of differential I/O’s.
The CRU has the option of either using the CMU’s reference clock or its own independent reference clock
“CRUREFCLK”. This is accomplished with the control signal “CRUREFSEL”. The “CRUREFCLK” should be
used if the system is being operated in either a regeneration or looptiming mode. In either of these modes the
quality of the “CRUREFCLK” is not a concern, thus it can be driven by a simple 77.76MHz crystal, the key is
its’ independent of the CMU’s reference clock.
Table 1: Recommended External Capacitor Values
Reference
Frequency
[MHz]
19.44
77.76
Divide Ratio
32
8
CP
0.1
0.1
CN
0.1
0.1
Type
X7R
X7R
Size
0603/0805
0603/0805
Tol.
+/-10%
+/-10%
Figure 6: External Integrator Capacitor
CP = 0.1
µF
CP1
CP2
+
-
CN1
CN2
CN = 0.1
µF
G52221-0, Rev. 4.1
1/8/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
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