VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8117
Table 7: Receive Data Output Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLKIN
TRXLSCKT
Receive clock period
-
-
6.43
-
-
ns
ns
Receive data output byte clock period
51.44
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
TRXVALID
TPW
22
-
-
-
-
ns
ns
Pulse width of frame detection pulse FP
51.44
Data Latency
The VSC8117 contains several operating modes, each of which exercise different logic paths through the
part. Table 10 bounds the data latency through each path with an associated clock signal.
Table 8: Data Latency
Clock
Reference
Range of Clock
cycles
Circuit Mode
Description
Receive
MSB at RXDATAIN to data on RXOUT [7:0]
MSB at RXDATAIN to MSB at TXDATAOUT
RXCLKIN
RXCLKIN
25-35
2-4
Facilities
Loopback
Clock Recovery Unit
Table 9: Reference Frequency for the CRU
CRUREFCLK
Frequency
[MHz]
Output
Frequency
[MHz]
CRUREFSEL
STS12
1
1
0
1
77.76 ± 500ppm
77.76 ± 500ppm
622.08
155.52
0
Uses CMU’s Reference Clock (See Table 10 below)
Clock Multiplier Unit
Table 10: Reference Frequency Selection and Output Frequency Control
Reference
Output
STS12
CMUFREQSEL
Frequency
[MHz]
Frequency
[MHz]
1
1
0
0
1
0
1
0
19.44
77.76
19.44
77.76
622.08
622.08
155.52
155.52
G52221-0, Rev. 4.1
1/8/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
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