VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8117
CRU clock and data signals. (In this mode the VSC8117 operates just like the VSC8111 and VSC8116). The
receive section also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during
the A1, A2 boundary in the serial to parallel converter. This only occurs when OOF is high. Both internal and
external LOS functions are supported. The high speed serial signals can be made PECL compatible or LVPECL
compatible by setting the proper voltage on the V
DDP
supply pins
VSC8117 Block Diagram
EQULOOP
DSBLCRU
D Q
1
RXDATAIN+/-
CRUEQLP
RXCLKIN+/-
0
CRU
REC-CLK
REC-DATA
FRAMER
OOF
FP
8
0
1
0
1
0
0
1
0
1
1:8
DEMUX
D Q
RXOUT[7:0]
1
Divide-by-8
RXLSCKOUT
LOSPECL
LOSDETEN_
losdet
0
CRUREFCLK
1
1
CRUREFSEL
0
CMU
STS12
REFCLKP+/-
REFCLK
CMUFREQSEL
LOOPTIM0
TXDATAOUT+/-
Q D
1
0
1
0
Divide-by-8
TXLSCKOUT
8:1
MUX
Q D
8
TXIN[7:0]
FACLOOP
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
