VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
VSC8115
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation
2
2
DATAIN+/-
DATAOUT+/-
PLL Clock
(on-chip)
REFCLK
STS12
BYPASS
0
1
2
CLKOUT+/-±
LOCKREFN
SD
LOS
(on-chip)
Table 1: Signal Detection and PLL Bypass Operation Control
STS12
1
1
1
1
1
0
0
0
0
0
BYPASS
0
0
0
0
1
0
0
0
0
1
LOCKREFN
1
1
0
0
X
1
1
0
0
X
SD
1
0
1
0
X
1
0
1
0
X
LOS
0
1
1
1
0
0
1
1
1
0
DATAOUT
DATIN
LOW
LOW
LOW
DATIN
DATIN
LOW
LOW
LOW
Not Allowed
CLKOUT
PLL Clock
PLL Clock
PLL Clock
PLL Clock
REFCLK
PLL Clock
PLL Clock
PLL Clock
PLL Clock
Not Allowed
G52272-0, Rev. 1.1
9/29/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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