VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Layout of the High Speed Signals
The routing of the High Speed signals should be done using good high speed design practices. This would
include using controlled impedance lines and keeping the distance between components to an absolute mini-
mum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help min-
imize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the
output pull down resistor should be placed as close to the VSC8113 pin as possible while the AC-coupling
capacitor and the biasing resistors should be placed as close as possible to the optics input pin. The same is true
on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing dis-
continuities.
Ground Planes
The ground plane for the components used in the High Speed interface should be continuous and not sec-
tioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to inter-
fere with the ground return currents on the signal lines. In addition, the smaller the ground planes the less
effective they are in reducing ground bounce noise and the more difficult to decouple. Sectioning of the positive
supplies can provide some isolation benefits.
Figure 13: AC Coupled High Speed I/O
VSC8113
PECL I/O
+3.3V
+5.0V
DRIVER
RECEIVER
(Optics Module)
(Optics Module)
R3
C1
C2
PC Board Trace
PC Board Trace
R2
GND
R4
GND
R1
GND
GND
Note: Only one side of a differential signal is shown.
Table 19: AC Coupling Component Values
Component
Value
Tolerance
R1
270 ohms
75 ohms
5%
5%
1%
1%
R2
R3
R4
68 ohms
190 ohms
C1, C2, C3, C4
.01uf High Frequency
Page 26
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52154-0, Rev 4.2
3/19/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
