VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore 3 ns of the
max delay is due to loading. The VSC8113 input (TXLSCKIN) plus package is about 6pf. Assuming about 1 pf/
inch of 75 ohm trace on FR4 plus the VSC8113 6pf load, the user would in most cases choose option 1.
DC Coupling and Terminating High-speed PECL I/Os
The high speed signals on the VSC8113 (RXDATAIN, RXCLKIN, TXDATAOUT, TXCLKOUT, REF-
CLKP, LOSPECL) use 3.3/5V programmable PECL I/Os which can be direct coupled to either +3.3V PECL or
+5V PECL signals from the optics. These PECL levels are essentially ECL levels shifted positive by 3.3 volts or
5 volts. These PECL I/Os are referenced to the V
supply (VDDP) and are terminated to ground. To program
DDP
these I/Os for either 3.3V or 5V interface, the 3 V
supplies accordingly.
pins (pin 9, 15, 21) are required to connect to 3.3V or 5V
DDP
AC Coupling and Terminating High-speed PECL I/Os
If the optics modules provide ECL level interface, the high speed signals can be AC coupled to the
VSC8113 as well. The PECL receiver inputs of the VSC8113 are internally biased at VDD/2. Therefore, AC-
coupling to the VSC8113 inputs is accomplished by providing the pull-down resistor for the open-source PECL
output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor
allows the PECL receivers of the VSC8113 to self-bias via its internal resistor divider network (see Figure 13).
The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output
level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off.
Since VDD-2.0V is usually not present in the system, the resistor could be terminated to ground for conve-
nience. The VSC8113 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics mod-
ule, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should
be employed.
The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin
equivalent circuit as shown in Figure 14. The figure shows the appropriate termination values when interfacing
3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os
and also provides the required dc biasing for the receivers of the optics module. Table 18 contains recommended
values for each of the components.
TTL Input Structure
The TTL inputs of the VSC8113 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol-
erances (see Table 5). The input structure, shown in Figure 14, uses a current limiter to avoid overdriving the
input FETs.
G52154-0, Rev 4.2
VITESSE SEMICONDUCTOR CORPORATION
Page 25
3/19/99
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
