t
C
CLKI (1() CLKIN)
High speed differential clock input
t
OOFNPW
OOFN
t
Frame recovery clock input
OOFN
SONET STS-3 Framing Sequence
DATA
DI (DIN)
High speed serial data inputs
DATA
DATA
DATA
DATA
A1
A1
A1
A2
A2
A2
t
D
BYCKO (BYCKON)
Byte clock output
BYCKO Resynch
t
BD
D1 (D1N)
D2 (D2N)
D3 (D3N)
D4 (D4N)
D5 (D5N)
D6 (D6N)
D7 (D7N)
D8 (D8N)
Valid
Valid
Valid
Data
Data
Data
Valid
Valid
Valid
Data
Data
Data
Valid
Valid
Valid
Valid
Valid
Data
Data
Data
Data
Data
Valid
Valid
Valid
Valid
Valid
Data
Data
Data
Data
Data
(2)
Parallel Data•
Output Summary
Data Data Data Data
A1
A1
A2
A2
A2
t
t
DFP
PFP
FP
Frame detection confirm output
NOTES:
1) Negative edge is active edge.
2) The parallel data outputs only begin showing valid data after the last A2 of the SONET framing sequence. The example
waveforms shown above use an STS-3 framing sequence for convenience, thus valid data is output after the third
A2 in the sequence.
= Don’t care.
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
