VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
SONET/SDH 3.125Gb/s
Laser Diode Driver with Automatic Power Control
VSC7940
Reducing Pattern-Dependent Jitter
Three design values significantly affect pattern-dependent jitter; the capacitor at CAPC, the pull-up induc-
tor at the output (LP), and the AC-coupling capacitor at the output (CD). As previously stated, the recommended
value for the capacitor at CAPC is 0.1µF. This results in a 10kHz loop bandwidth which makes the pattern-
dependent jitter from the APC loop negligible.
For 2.5Gb/s data rates, the recommended value for CD is 0.056µF. The time constant at the output is domi-
nated by L . The variation in the peak voltage should be less that 12% of the average voltage over the maximum
P
consecutive identical digit (CID) period. The following equation approximates this time constant for a CID
period, t, of 100UI = 40ns:
τ
LP = -t / ln(1-12%) = 7.8t = LP / 25Ω
Therefore, the inductor L should be a 7.8µH SMD ferrite bead inductor for this case.
P
Input/Output Considerations
Although the VSC7940 is PECL-compatible, this is not required to drive the device. The inputs must only
meet the common-mode voltage and differential voltage swing specifications.
Power Consumption
The following equation provides the device supply current (IS) in terms of quiescent current (IQ), modula-
tion current (I
), and bias current (I
):
MOD
BIAS
IS = 19mA + 0.4 * IMOD + 0.16 * IBIAS
This equation may be used to determine the estimated power dissipation:
DIS = VCC * IS
P
For example, if the device were operated at 5V with a 30mA modulation current and a 10mA bias current,
the supply current would be:
IS = 19mA + 0.4 * 30mA + 0.16 * 10mA = 33mA
This corresponds to a power dissipation of 5V * 33mA = 165mW.P
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