ESE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
Loopback Operation
Loop back control pins, LBEN(1:0), are provided to internally loopback data paths for on-chip diagnosis.
Both serial and parallel loopback functions are provided.
Table 8: Loopback Mode Selection
LBEN(1:0)
Loopback Mode
Normal Operation
0 0
0 1
1 0
1 1
Internal Parallel Loopback
Internal Serial Loopback
Reserved
When LBEN(1:0)=10, Serial Loopback mode is selected. The transmitter’s serial transmit data is internally
connected to the receiver’s CRU input. The serial loopback paths are labelled LBTX in the VSC7212 block
diagram on the first page. This allows parallel data on T(7:0) to be encoded, serialized, looped back,
deserialized and decoded. This mode is intended for the system to verify functionality of the local VSC7212
prior to attempting to establish an external link. The PTX and RTX outputs are unaffected by the state of
LBEN(1:0).
When LBENn(1:0)=01, Parallel Loopback mode is selected. The R(7:0) outputs are looped back to the
T(7:0) inputs (see Figure 11). WSEN does not have a loopback source and is internally connected to a logic
LOW. KCHAR does not have a loopback source and is internally connected to a logic HIGH. The C/D input is
obtained by decoding the link status outputs such that either a data character, special character, or IDLE (K28.5)
is transmitted. When the link is in the LOS or RESYNC states, C/D is asserted and the data path is set to 0xBC
so that an IDLE will be transmitted. For other link status conditions C/D follows the KCH status bit. This
guarantees that IDLE and special characters will be correctly looped back along with normal data, and also has
the effect of looping back the data received as a normal data character when a disparity error, out-of-band
character, or underflow/overflow link status condition occurs.
In Parallel Loopback mode the receiver uses REFCLK as the word clock with RMODE(1:0) internally set
to 00. This data is looped back to the transmitter with TMODE(2:0) internally set to 000. This guarantees that
the parallel loopback data to be re-transmitted will be frequency locked to the transmitter’s REFCLK, but
means that the receiver parallel output data timing may not match the normal system timing that is externally
selected by RMODE(1:0). In this case, the parallel output data should be ignored.
This internal loopback configuration also allows rate matching to be performed in the receivers’ elastic
buffers. Rate matching is controlled and operates exactly the same way that it does in normal mode. This is
needed to avoid receiver Overrun/Underrun errors in the loopback device if the remote transmitting device’s
REFCLK is not frequency locked to the loopback device’s REFCLK. Keep in mind that the LBEN(1:0), RXP/
R, PTXEN, RTXEN and BIST inputs must all be configured appropriately in order for end-to-end parallel
loopback to function correctly in a user environment. Parallel Loopback mode is internally disabled when BIST
mode is enabled.
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Page 16
G52268-0, Rev 3.3
04/10/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
