VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
Gigabit Interconnect Chip
VSC7212
If RMODE1 is LOW and if the transmitting device’s REFCLK is not precisely frequency-locked to a
receiver’s REFCLK, then the channel’s elastic buffer will tend to gradually fill or empty as the recovered clock
(which is by definition frequency-locked to the transmitter’s REFCLK) steadily drifts in phase relative to the
word clock. In order to accommodate frequency differences between a transmitter’s REFCLK and the receiver’s
REFCLK, the VSC7212 can automatically perform “rate matching” by either deleting or duplicating IDLE
characters. FLOCK must be LOW and WSI must be connected to WSO to enable rate matching. It is the user’s
responsibility to ensure that the frequency at which IDLEs are transmitted accommodates the frequency
differences, if any, in their system architecture. Not meeting the IDLE density requirements described below
may result in Underrun/Overrun Errors.
The elastic buffer is designed to allow a maximum phase drift of +2 or -2 serial clock bit times between re-
synchronizations, which sets a limit on the maximum data “packet” length allowed between IDLEs. This
maximum packet length depends on the frequency difference between the transmitting and receiving devices
REFCLKs. Let ∆φ represent phase drift in bit times, and let 2π represent one full 10-bit character of phase
drift. Limiting phase drift to two bit times means the following inequality must be satisfied:
∆φ ≤ (0.2 × 2π)
(1)
Let L be the number of 10-bit characters transmitted, and let Df be the frequency offset in ppm. The total
phase drift in bit times is given by:
(2)
∆φ = (∆f ⁄ 106) × 2πL
A simple expression for maximum packet length as a function of frequency offset is derived by substituting
(2) in (1) and solving for L:
(3)
L ≤ (0.2 × 106) ⁄ ∆f
As an example, if the frequency offset is 200ppm, then the maximum packet length should not be more than
1K bytes. To increase the maximum packet length L, decrease the frequency offset Df. Note that if only one
K28.5 is transmitted between “packets” of data, it might be dropped during compensation for phase drift. If the
user must have at least one K28.5 between these two packets, then two K28.5s must be transmitted.
Using Multiple VSC7212s in Parallel
Multiple VSC7212s and VSC7216s can be used in parallel to form wider bus widths. In order for chip-to-
chip word alignment to function correctly across multiple devices, each transmit channel’s input data must be
transmitted synchronously to a common REFCLK or TBC, and each receiver’s output data must also be aligned
to a common REFCLK. This requires that all transmitting devices use either the same or identical REFCLKs,
and that TMODE(2:0)=000 (inputs timed to REFCLK) or TMODE(2:0)=1X0 (inputs timed to TBC). If inputs
are timed to TBC, then all transmitting devices must use either the same or identical TBCs. Since all receive
channels must use a common word clock, the receiving devices must also use the same or identical REFCLKs
and it must be selected as the word clock for all receive channels (RMODE(1:0)=0X).
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52268-0, Rev 3.3
04/10/01
Page 11
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