®
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7182
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Loopback Operation
Loopback operation is controlled by the PLUP (Parallel Loopback), SLPN (Serial Loopback) and LPNi
inputs as shown in Table 2. LPNi enables PLUP/SLPN on a per-channel basis when LOW. If LPNi is HIGH,
PLUP/SLPN have no impact on Channel x. When SLPN and PLUP are both HIGH the transmitter output is
held HIGH. When RXx is looped back to TXx, the data goes through a clock recovery unit so much of the
input jitter is removed. However, the TXx outputs may not meet jitter specifications listed in the “Transmitter
AC Specifications” due to low frequency jitter transfer from RXx to TXx.
Table 2: Loopback Selection
LPNi
LOW
LOW
LOW
LOW
HIGH
PLUP
LOW
LOW
HIGH
HIGH
X
SLPN
LOW
HIGH
LOW
HIGH
X
Tranmitter Source
Receiver
Transmitter
Transmitter
HIGH
Transmitter
Receiver Source
Receiver
Receiver
Transmitter
Transmitter
Receiver
JTAG Access Port
A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in “VSC7182 JTAG Access Port Functionality.”
G52307-0, Rev 2.2
10/10/00
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VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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