®
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7182
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Serializer
The VSC7182 accepts TTL input data as a parallel 10-bit character on the TXi[0:9] bus which is latched
into the input register on the rising edge of either RFC or TCi. Three clocking modes are available and automat-
ically detected by the VSC7182. If TCC is static and RFCM is HIGH, then all four TXi[0:9] busses are latched
on the rising edges of RFC. If TCC is static and RFCM is LOW, then RFC is multiplied by 20 and the input bus-
ses are latched on the rising edges of RFC and at the midpoint between rising edges. If TCC is toggling but TCB
is static, then all four TXi[0:9] busses are latched on the rising edges of TCC. If TCB and TCC are both toggling
then the rising edge of each TCi latches the corresponding TXi[0:9] bus.
The active TCC or TCi inputs must be frequency-locked to RFC. There is no specified phase relationship.
Prior to normal data transmission, LTCN must be asserted LOW so the VSC7182 can lock to TCi, which may
result in corrupted data being transmitted. Once LTCN has been raised HIGH, the transmitters remain locked to
RFC and can tolerate +/-2 bit times of drift in TCi relative to RFC.
The 10-bit parallel transmission character will be serialized and transmitted on the TXi PECL differential
outputs at the baud rate with bit TXi0 (bit A) transmitted first. User data should be encoded using 8B/10B or an
equivalent code. The mapping to 10B encoded bit nomenclature and transmission order is illustrated below,
along with the recognized comma pattern.
Table 1: Transmission Order and Mapping of a 10B Character
Data Bit
10B Bit Position
Comma Character
TXi9
j
x
TXi8
h
x
TXi7
g
x
TXi6
f
1
TXi5
i
1
TXi4
e
1
TXi3
d
1
TXi2
c
1
TXi1
b
0
TXi0
a
0
Clock Recovery
The VSC7182 accepts differential high-speed serial input from the selected source (either the PECL SI+/
SI- pins or the internal TXi+/- data), extracts the clock and retimes the data. Equalizers are included in the
receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the
incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by
an 8B/10B encoding scheme. The digital Clock Recovery Unit (CRU) is completely monolithic and requires no
external components. For proper operation, the baud rate of the data stream to be recovered should be within
+200 ppm of ten times the RFC frequency. For example, Gigabit Ethernet systems would use 125MHz oscilla-
tors with a +100ppm accuracy resulting in +200 ppm between VSC7182 pairs.
Deserializer
The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7182 provides
complementary TTL recovered clocks, RCi0 and RCi1, which are at 1/20
th
of the serial baud rate (if
RCM=LOW) or 1/10
th
(if RCM=HIGH). The clocks are generated by dividing down the high-speed recovered
clock which is phase-locked to the serial data. The serial data is retimed, deserialized and output on RXi[0:9].
If serial input data is not present, or does not meet the required baud rate, the VSC7182 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency
under these circumstances will differ from its expected frequency by no more than +1%. A receiver squelch cir-
cuit forces the parallel data output bus to all ones if the serial receiver input level is less than 100mV differential
peak-to-peak.
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52307-0, Rev 2.2
10/10/00
Page 3
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
