VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
VSC7139
Pin
Name
Description
INPUT - TTL: Serial Loopback enable input. Normal operation when HIGH. When
LOW, Rx+/- is looped back to Tx+/- internally for diagnostic purposes. Refer to Table 2
and related description.
C9
SLPN
R3
P4
K4
D5
LPNA
LPNB
LPNC
LPND
INPUT - TTL: Loopback Enable Pins. When LPNx is LOW, PLUP/SLPN impact
Channel x. When HIGH, PLUP/SLPN have no effect on Channel x.
INPUT - TTL: Enables SYNCx and word alignment when HIGH. When LOW, keeps
current word alignment and disables SYNCx (always LOW).
R17
ENCDET
F2
A4
B10
B15
SYNCA
SYNCB
SYNCC
SYNCD
OUTPUT - TTL: Comma Detect for Channel x. This output goes HIGH for half of an
RCx1 period to indicate that Rx(0:9) contains a Comma Character (‘0011111XXX’).
SYNCx will go HIGH only during a cycle when RCX0 is rising. SYNCx is enabled when
ENCDET is HIGH.
P9
R9
CAP0
CAP1
ANALOG: Loop Filter capacitor for the Clock Multiply Unit. Typically 0.1 uF connected
between CAP0 and CAP1. Amplitude is less than 3.3V.
T17
D9
TCK
TMS
INPUT - TTL: JTAG Test Clock
INPUT - TTL: JTAG Test Mode Select
INPUT - TTL: JTAG Test Reset, Active Low
INPUT - TTL: JTAG Test Data Input
OUTPUT - TTL: JTAG Test Data Output
Analog Power Supply
R15
P15
K2
TRSTN
TDI
TDO
T9
VDDA
VSSA
R8
Analog Ground. Tie to common ground plane with VSS.
A2,A10,C14
G4,J14,K16
L4,N15,R4
R14,T3
VDD
Digital Logic Power Supply
T4,T14,U5
C4, D3,F3
A9, B7, C5
A13, A16, C11
C15, E14, G17
VDDT
TTL Output Power Supply.
T5
T7
T11
T13
VDDPA
VDDPB
VDDPC
VDDPD
PECL I/O Power Supply for Channel x.
R16
T16
VDDTR
VSSTR
TTL Output Power Supply for RFCO0 and RFCO1
TTL Ground for RFCO0 and RFCO1
A1,A3,A11,A15
A17,B4,C7
C16,D4,D11
E15,F4
VSST
Ground for TTL Outputs
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 14
G52196-0, Rev 3.3
5/14/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
