VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
Quad Transceiver for
Gigabit Ethernet and Fibre Channel
VSC7139
Pin
Name
Description
R5, P5
R7, P7
P11, R11
P13, R13
TA+, TA-
TB+, TB-
TC+, TC-
TD+, TD-
OUTPUT - Differential PECL (AC Coupling recommended)
These pins output the serialized transmit data for Channel x when PLUP is LOW. When
PLUP is HIGH, Tx+ is HIGH and Tx- is LOW.
D1, D2, E3
E4, C1, C2
C3, B1, B2
B3
RA0, RA1, RA2
RA3, RA4, RA5 OUTPUT - TTL: 10-bit Receive bus for Channel A. Parallel data on this bus is
RA6, RA7, RA8 synchronous to RCA0 and RCA1. RA0 is the first bit received.
RA9
A6, B6, C6
D6, A7, D7
A8, B8, C8
D8
RB0, RB1, RB2
RB3, RB4, RB5 OUTPUT - TTL: 10-bit Receive bus for Channel B. Parallel data on this bus is
RB6, RB7, RB8 synchronous to RCB0 and RCB1. RB0 is the first bit received.
RB9
B11, A12, B12
C12, D12, B13
C13, D13, A14
B14
RC0, RC1, RC2
RC3, RC4, RC5 OUTPUT - TTL: 10-bit Receive bus for Channel C. Parallel data on this bus is
RC6, RC7, RC8 synchronous to RCC0 and RCC1. RC0 is the first bit received.
RC9
C17, D14, D15
D16, D17, E16
E17, F14, F15
F16
RD0, RD1, RD2
RD3, RD4, RD5 OUTPUT - TTL: 10-bit Receive bus for Channel D. Parallel data on this bus is
RD6, RD7, RD8 synchronous to RCD0 and RCD1. RD0 is the first bit received.
RD9
INPUT - TTL: Recovered clock MODE control. When LOW, RCx0/RCx1 is 1/20th of the
T1
RCM
incoming baud rate. When HIGH, RCx0/RCx1 is 1/10th the incoming baud rate.
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel A at 1/
E1
E2
RCA0
RCA1
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RA(0:9) and SYNCA bus.
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel B at 1/
A5
B5
RCB0
RCB1
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RB(0:9) and SYNCB bus.
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel C at 1/
C10
D10
RCC0
RCC1
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RC(0:9) and SYNCC bus.
OUTPUT - Complementary TTL: Recovered complementary clocks for Channel D at 1/
B16
B17
RCD0
RCD1
10th the incoming baud rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous to the
RD(0:9) and SYNCD bus.
U4, U3
U7, U6
U11, U10
U14, U13
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
INPUT - Differential PECL (AC Coupling recommended): Serial receive data inputs for
Channel x which are selected when PLUP is LOW. [Internally biased to VDD/2]
INPUT - TTL: Parallel Loopback Enable input. Rx is input to the CRU for Channel x
(normal operation) when PLUP is LOW. When HIGH, internal loopback paths from Tx
to Rx are enabled. Refer to Table 2.
N14
PLUP
G52196-0, Rev 3.3
5/14/01
Page 13
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