VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre
Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Figure 4: Transmit Timing Waveforms
AC Characteristics
REFCLK
T
1
T
2
T(0:9)
Data Valid
Data Valid
Data Valid
Table 2: Transmit AC Characteristics
Parameters
T
1
T
2
T
SDR
,T
SDF
T
LAT
Description
T(0:9) Setup time to the
rising edge of REFCLK
T(0:9) hold time after the
rising edge of REFCLK
TX+/TX- rise and fall time
Latency from rising edge of
REFCLK to T0 appearing on
TX+/TX-
Total data output jitter
Serial data output
deterministic jitter (p-p)
Min
1.5
Max
—
Units
ns.
Conditions
Measured between the valid
data level of T(0:9) to the 1.4V
point of REFCLK
1.0
—
—
300
8bc+
4ns
ns.
ps.
20% to 80%, 50 Ohm load to
V
DD
-2.0
bc = Bit clocks
ns = Nano second
8bc
ns
Transmitter Output Jitter Allocation
T
J
T
DJ
—
—
192
80
ps.
ps.
IEEE 802.3z Clause 38.68,
IEEE 802.3z Clause 38.68,
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52187-0 Rev. 2.4
1/17/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
