VITESSE
SEMICONDUCTOR CORPORATION
10-bit Transceiver for Fibre
Channel and Gigabit Ethernet
Advance Product Information
VSC7133
Functional Description
Clock Synthesizer
The VSC7133 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock between 0.98 and 1.36 GHz. The on-chip PLL uses a single external 0.1uF capacitor
to control the Loop Filter. The REFCLK is either TTL or LV PECL. If TTL, connect the TTL input to
REFLKP and leave REFCLKN open, it is biased for a TTL switch level. If PECL, connect both REFCLKP and
REFCLKN.
Serializer
The VSC7133 accepts TTL input data as a parallel 10 bit character on the T(0:9) bus, which is latched into
the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL differ-
ential outputs at a baud rate that is ten times the frequency of the REFCLK, with bit T0 transmitted first. User
data should be encoded using 8B/10B block code or equivalent.
Transmission Character Interface
An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the
VSC7133 corresponds to a transmission character. This mapping is illustrated in Figure 1.
Figure 1: Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits
8B/10B Bit Position
Comma Character
T9
j
X
T8
h
X
T7
g
X
T6
f
1
T5
i
1
T4
e
1
T3
d
1
T2
c
1
T1
b
0
T0
a
0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery
The VSC7133 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol
Interference (ISI) which may be present in the incoming data. The serial bit stream should be encoded so as to
provide DC balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit (CRU) is
completely monolithic and requires no external components. For proper operation, the baud rate of the data
stream to be recovered should be within +200 ppm of ten times the REFCLK frequency. For example, Gigabit
Ethernet systems would use 125 MHz oscillators with a +/-100ppm accuracy resulting in +/-200 ppm between
VSC7133 pairs.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52187-0 Rev. 2.4
1/17/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
