VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
VSC7127/VSC7129
Figure 4: REFCLK Timing Waveforms *
V
IH(MIN)
REFCLK
V
IL(MAX)
NOTE: A reference clock must be provided to the REFCLK pin in order for the chip to power up in the right state.
Table 2: Reference Clock Requirements
Parameters
Description
Frequency Range
Min
Typ
Max Units
Conditions
FR
105
107
MHz
Maximum frequency offset
between transmit and receive
reference clocks on one link
FO
Frequency Offset
-200
35
200
ppm
DC
Duty Cycle
65
%
ns
Measured at 1.5V
TR, TF
Rise and Fall Time
2.0
Between VIL(MAX) and VIH(MIN)
DC Characteristics (Over recommended operating conditions)
Parameters
Description
Min
Typ
Max
Units
Conditions
VOH
VOL
VIH
VIL
IIH
Output HIGH voltage (TTL)
Output LOW voltage (TTL)
Input HIGH voltage (TTL)
Input LOW voltage (TTL)
Input HIGH current (TTL)
Input LOW current (TTL)
2.4
V
V
IOH = -1.0mA
IOL = +1.0mA
0.5
5.5
2.0
0
V
0.8
V
50
500
-500
µA
µA
VIN =2.4V
VIN =0.5V
IIL
TX output differential peak-to-
peak voltage swing
(1)
∆VOUT75
1200
1000
2200
2200
mVp-p 75Ω to VDD – 2.0 V
mVp-p 50Ω to VDD – 2.0 V
mVp-p Internally biased to VDD/2
TX output differential peak-to-
peak voltage swing
(1)
∆VOUT50
Receiver differential peak-to-peak
input Sensitivity RX
(1)
∆VIN
400
2600
3.47
902
VDD
PD
Supply voltage
3.14
V
3.3V±5%
Outputs open, VDD = VDD max.
±2%
Power dissipation
Current (all supplies)
707
mW
IDD
215
50
260
70
mA
mA
Outputs open, VDD = VDD max
VDDA = VDD max
IDDA
Current (VDDA)
NOTE: (1) Refer to Application Note AN-37 for details regarding differential voltage measurements.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 6
G52298-0, Rev 4.3
05/01/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
