VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
VSC7127/VSC7129
Fill Word or Primitive Sequence. Any Fill Word or Primitive Sequence will reset the OSSDU counter which
will increment on any 160-bit sequence which is not a Fill Word or Primitive Sequence. If the counter reaches
256, a Fill Word or Primitive Sequence has not occured often enough so OSSDU is asserted until reset again.
SIGDET is just an or’ing of these three state machines resynchronized to the 160-bit interval clock.
If SEL5 is LOW or REFCLK is absent, the signal detect unit is disabled and SIGDET is LOW.
Application Example
Figure 2 shows one loop of an 8-drive JBOD implemented with two VSC712xs per loop. The input from
the connector goes through a repeater in order to clean up the signal prior to the array of disk drives. After all
eight PBCs, the output the to connector is retimed to ensure jitter compliance at the connector.
Figure 2: 8-Drive JBOD
Drive 3
Drive 6
Drive 2
Drive 5
O2
O2
I2
I2
O3
I3
SEL2
O3
I3
SEL2
1
0
1
0
SEL3
O4
SEL3
O4
SEL1
SEL1
1
1
I1
I1
MODE=0
SEL0=1
MODE=1
SEL1=1
I4
I4
O1
O1
SEL4
SEL4
MODE
SEL0
MODE
SEL0
0
1
RPTR
RTMR
O0
O0
I0
I0
Drive 8
Connector
NOT SHOWN: PBC5, SEL5
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 4
G52298-0, Rev 4.3
05/01/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
