Advance Product Information
Subject to Change
VSC7111 Datasheet
Pin Descriptions
Table 61.
Control Pins (continued)
Signal Name Pin Number I/O Signal Level Description
IFMODE1
3
I
LVTTL
11: Static mode
10: Two-wire serial master
01: Four-wire serial slave
00: Two-wire serial slave
LOPWR
2
9
I
I
LVTTL
LVTTL
1: 6.5 Gbps mode
0: Full power 11.5 Gbps mode
MUXCFG
1: MUX/fanout mode (one input to two
outputs)
0: Buffer mode An to Yn
SA0
31
30
1
I
I
LVTTL
LVTTL
LVTTL
Two-wire serial address bit 0; TX EQ bit 0
in static mode
SA1
Two-wire serial address bit 1; TX EQ bit 1
in static mode
SA2_MISO
B
Four-wire serial data output; two-wire
serial address bit 2; RX EQ bit 1 in static
mode
SA3_SSB
SCK
23
32
I
I
LVTTL
LVTTL
Two-wire serial address bit 3; four-wire
serial chip select active low; RX EQ bit 2 in
static mode
Serial interface clock in two-wire and
four-wire modes.
Static buffer mode (MUXCFG = 0):
1: PCIe mode
0: Normal mode
Static select/fanout mode (MUXCFG = 1):
1: Select odd inputs
0: Select even inputs
SDA_MOSI
TESTMD
10
11
B
I
LVTTL
LVTTL
Two-wire serial data I/O; four-wire serial
data input; RX EQ bit 0 in static mode
1: Vitesse test mode
0: Normal operation
5.2.4
Power Supplies
The following table lists the power supply pins.
Power Supply Pins
Table 62.
Signal Name Pin Number Description
VDD
VSS
6, 14, 19, 27 Power supply
Center pad Ground. Center pad must be connected to ground.
Revision 2.0
September 2010
Confidential
Page 51
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
