VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
SMPTE-292M Serializer, Deserializer, and
Deserializer/Reclocker at 1.485Gb/s
VSC6511
Figure 8: REFCLK Timing Waveforms: All Modes
T
T
H
L
VIH(MIN)
VIL(MAX)
REFCLK
T
R
Table 6: Reference Clock Requirements *
Parameters
Description
Frequency Range
Min
Max
Units
Conditions
FR
73.75
74.50
MHz
Will accept both 74.176/74.25MHz
Difference in REFCLK frequencies
between the transmitting and
receiving VSC6511s.
FO
Frequency Offset
-1000
1000
ppm.
DC
REFCLK duty cycle
REFCLK high/low times
REFCLK rise
-15
3.0
—
+15
—
%
Measured at 1.5V
y
Measured between VIL(MAX) to
VIL(MAX) or VIH(MIN) to VIH(MIN)
TH, TL
TR
ns.
2.0
ns.
Between VIL(MAX) and VIH(MIN)
Note: The PLL locks to the rising edge of REFCLK.
tCop
Figure 9: RCLK Timing Waveforms*
T
T
H
L
Draf
VIH(MIN)
VIL(MAX)
RCLK
T
R
Table 7: RCLK Performance - Deserializer and Deserializer/Reclocker Mode
Parameters
Description
Min
Max
Units
Conditions
RCLK Frequency offset from
REFCLK
Maximum deviation when the CRU is
not locked. Deserializer Mode.
-1.0
+1.0
%
FOFFSET
Measured at 1.5V. Deserializer Mode
and Deserializer/Reclocker Mode.
-5
3
+5
—
%
DC
TH
RCLK duty cycle - 40% / 60%
RCLK high times
Measured between VIH(MIN) to
VIH(MIN)
ns.
Measured between VIL(MAX) to
VIL(MAX)
5.9
—
—
ns.
ns.
TL
TR
RCLK low times
1.5
RCLK rise/fall time
Between VIL(MAX) and VIH(MIN)
Note: The RCLK output from the CRU is 40% high and 60% low by design.
G52311-0, Rev. 2.0
4/10/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 13
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