VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
SMPTE-292M Serializer, Deserializer, and
Deserializer/Reclocker at 1.485Gb/s
VSC6511
Functional Description: Deserializer Mode
The following functional blocks are used in the Deserializer mode of operation. Please refer to the Func-
tional Description at the beginning of this document for the a description of each of these blocks.
Clock Multiplier Unit (CMU)
Serial Input
Clock Recovery Unit
Deserializer
Descrambler and NRZI Decoder
CRC Checker
Frame Aligner and SAV/EAV output
Figure 6: Receive Timing Waveforms (Deserializer Mode)
y
RCLK
T
T
2
D[0:19]
LINE
1
tCop
Data Valid
FRAME
CRCERR
Draf
Table 5: Receive AC Characteristics (Deserializer Mode)
Parameters
T1
Description
Min.
Max.
Units
Conditions
TTL Outputs alid prior to
RCLK rise
3.0
—
ns.
TTL Outputs valid after
RCLK rise
T2
2.0
—
—
—
2.0
ns.
ns.
TTL Output rise and fall
time
Between VIL(MAX) and
VIH(MIN), into 10 pf. load.
TR, TF
TLOCK
Data acquisition lock time
@ 1.485 Gb/s
TBC
ms.
Note: The RCLK output from the CRU is 40% high and 60% low by design.
G52311-0, Rev. 2.0
4/10/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
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