VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
500 Mb/s Video
Shift Register IC
VSC6424
Table 6: Timing Tables
Parameter
Description
Min
Typ
Max
Units
tcyci
tcyce
tdis
Minimum cycle time in internal timing mode
Minimum cycle time in external timing mode
DIN setup time
2.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
-
200
900
600
800
100
1200
1100
1200
1300
-140
-50
-
tdih
tsbcs
tsbch
tsbls
tsblh
tcco
tcdn
tcdi
DIN hold time
-
SB setup with respect to CLK
SB hold time with respect to CLK
SB setup with respect to LLD
SB hold with respect to LLD
CLK to CLKOUT delay
CLK rising to DOUT, with OPS low
CLK falling to DOUT, with OPS high
CLKOUT to DOUT skew, with OPS low
CLKOUT to DOUT skew, with OPS high
OEN to DOUT
-
-
-
-
3500
3700
3900
tccdn
tccdi
toed
tdds
tas
1100
1200
900
-
3000
DOUT<x> to DOUT<y> skew
A<0:4> setup time
100
1100
200
900
600
1000
200
1300
100
800
300
700
300
1700
1500
400
-
tah
A<0:4> hold time
-
taes
AEN setup time
-
taeh
tbls
AEN hold time
-
H/VBLANK setup
-
tblh
tslds
tsldh
tsys
H/VBLANK hold
-
SLDN setup
-
SLDN hold
-
SYNC setup
-
tsyh
tsis
SYNC hold
-
SIN setup
-
tsih
SIN hold
-
tcsb
tc-ce
tce-ct
CLK to SB delay
5800
5200
2500
CLK to CLKE delay
CLKE to CLKT skew
Page 12
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52236-0, Rev 3.0
7/13/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
