VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
500 Mb/s Video
Shift Register IC
VSC6424
Table 10: Package Pin Identification
Signal
Pin
I/O Level
Description
Shift enable. In external timing mode, SEN high stops
the shift register from shifting. In internal timing
mode, DIVC high divides the output clocks (CLKE,
CLKT)by 2.
SEN
DIVC
63
I
ECL
Output Enable. OEN high forces the DOUT<0:7> low.
This signal is asynchronous.
OEN
107
99
I
I
I
ECL
TTL
TTL
INT
EXTN
Timing control. A high sets the chip for internal
timing, a low sets the chip for external timing.
Address pins. These pins get transferred to
DOUT<0:7> in Address Interface mode.
A<0:4>
2, 1, 128, 127, 126
HBLANK
VBLANK
124
125
I
I
TTL
TTL
Horizontal blank function. Active low.
Vertical blank function. Active low.
Clock phase select. When this signal is low the low
speed outputs (DOUT<0:7>) are clocked with the
rising edge of the clock. Setting it high clocks them
with the falling edge of the clock.
OPS
35
I
TTL
CLKOUT
78
79
O
O
ECL
ECL
High speed clock out (True)
CLKOUTN
High speed output clock (Complement)
Page 16
VITESSE SEMICONDUCTOR CORPORATION
G52236-0, Rev 3.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
7/13/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
